The present invention relates to solid-state imaging apparatus having photoelectric conversion device, and more particularly relates to the solid state imaging apparatus where all pixel signals are read out at high rate with setting a certain exposure time so that image having high S/N can be acquired.
It is known to construct solid-state imaging apparatus such that photoelectric conversion sections of all pixels are concurrently reset to start accumulation of signal, and after concurrently transferring signals of the photoelectric conversion sections of all pixels to memory after a predetermined time, the signals are sequentially read out. In such a solid-state imaging apparatus, retaining time of signal at memory is different from one pixel row to another. For this reason, leak current occurring at memory and electric charge occurring due to leakage of light shed on memory are different between each pixel row depending on such retaining period, and thus become cause of shading.
To mitigate this, Japanese Patent Application Laid-Open Publication 2006-10889 for example has proposed a solid-state imaging apparatus where elimination of shading is made possible by subtraction between the pixel signals of a first row or column and the pixel signals of a second row or column. FIG. 1 is a diagram showing construction of the solid-state imaging apparatus disclosed in the publication, and FIG. 2 is a timing chart for explaining its operation. The construction of the solid-state imaging apparatus disclosed in the above publication will now be described by way of FIG. 1.
Provided at the inside of pixel PIX11 are: a photoelectric conversion section PD11; a memory C11 (hereinafter referred simply to as FD) for accumulating signal generated at the photoelectric conversion section PD11; a transfer switch MT11 for controlling transfer from the photoelectric conversion section PD11 to FD; a reset switch MR11 for resetting FD; an amplification section MA11 for amplifying signal of FD; and a select switch MS11 for selecting the pixel. These are connected as shown in FIG. 1 to form a pixel. A plurality of pixels having such construction are two-dimensionally arranged (2 rows by 2 columns in the illustrated example) to form a pixel section. It should be noted that the constituent components of the other pixels PIX12, PIX21, PIX22 of the pixel section are denoted by those numerals that correspond to row and column of each pixel.
The transfer switches MT11, MT12 of pixels PIX11, PIX12 of the first row are controlled by transfer control signal φTX1 outputted from a vertical scanning circuit 101, and transfer switches MT21, MT22 of pixels PIX21, PIX22 of the second row are controlled by transfer control signal φTX2. The select switches MS11, MS12 of pixels PIX11, PIX12 of the first row are controlled by select control signal φSEL1, and the select switches MS21, MS22 of pixels PIX21, PIX22 of the second row are controlled by select control signal q SEL2. The pixel output signals of selected row are written to a line memory 102 through a vertical signal line 105. Subsequently, the output signals stored at the line memory 102 are read out by a horizontal scanning circuit 103. It should be noted that numeral 104 in FIG. 1 denotes a control section for controlling operation of the vertical scanning circuit 101 and line memory 102.
The operation of the solid-state imaging apparatus having such construction will now be described by way of a timing chart shown in FIG. 2. At first, transfer control signals φTX1, φTX2, and reset control signals φRST1, φRST2 are driven to high level to start concurrent reset of photoelectric conversion section PD and FD of all pixels. Next, transfer control signals φTX1, φTX2 are brought to low level to end reset period of the photoelectric conversion section PD so that accumulation of light signal is started. Next, reset control signals φRST1, φRST2 are brought to low level to end reset of FD. Subsequently, transfer control signal φTX1 to the pixels of the first row is driven to high level to end an accumulation period and effect transfer to FD of the accumulated electric charge of photoelectric conversion section PD of the pixels of the first row. The transfer control signal φTX2 to the pixels of the second row on the other hand maintains low level so as not to effect transfer to FD of the accumulated electric charge of photoelectric conversion section PD of the pixels of the second row. Next, pixel rows selected by select control signal in the manner of time series are sequentially read out. In particular at first, the select control signal φSEL1 is driven to high level to output pixel signals of the pixel (main pixel) row of the first row to the line memory 102 through the vertical signal line 105, and the select control signal φSEL1 is brought to low level to end the outputting. Next, select control signal φSEL2 is driven to high level to output pixel signals of the pixel (sub pixel) row of the second row to the line memory 102. These operations are sequentially continued.
The output signal of such main pixel row (first pixel row) becomes a signal where FD leak signal (referred to as Vsf in this description) and signal due to leakage light (referred to as Vse in this description), i.e. noise signals are added to light signal (referred to as Vp in this description) accumulated at the photoelectric conversion section. The output signal of the main pixel row supposed as Vs1 is represented in symbols as in the following equation (1).Vs1=Vp+Vsf+Vse  (1)
Further, the output signal of sub pixel row (second pixel row) becomes a signal where FD leak signal Vnf and signal by leakage light Vne, i.e. noise signals are added up so that the output signal of the sub pixel row supposed as Vn1 is represented in symbols as in the following equation (2).Vn1=Vnf+Vne  (2)
In this case, since the main pixel and the sub pixel are read out at substantially the same point in time, FD leak signal and signal due to leakage light are respectively of substantially the same value, and are represented in symbols as:Vsf=Vnf, Vse=Vne.Accordingly, difference between the main pixel signal and the sub pixel signal is obtained as:Vs1−Vn1=Vp 
Further, the disposition of main pixel 1 and sub pixel 2 in the pixel section may be as shown in FIG. 3 so that the main pixel 1 and sub pixel 2 are disposed at every other row.